In FIG. 1, a prior art example of a dedicated boundary scan path or register exists around a master circuit 102, a slave 1 circuit 104, and a slave 2 circuit 106. The master circuit, such as a DSP, CPU, or micro-controller, is a circuit that controls the slaves. The slave circuits are circuits being controlled by the master, such as RAM, ROM, cache, A/D, D/A, serial communication circuits, or I/O circuits. The master and slave circuits could exist as individual intellectual property core sub-circuits inside an integrated circuit or IC, or as individual ICs assembled on a printed circuit board or multi-chip module (MCM). The scan paths 108-112 around each circuit are connected together serially and to a test data input (TDI) 114, which supplies test data to the scan paths, and a test data output (TDO) 116, which retrieves data from the scan paths.
For simplification, only a portion of the scan paths 108-112 of each circuit is shown. The scan paths of FIG. 1 are designed using dedicated scan cells, indicated by capital letters (C) and (D) in circles. The word dedicated means that the cell's circuitry is used for testing purposes and is not shared for functional purposes. The scan cells are located between the internal circuitry and the input buffers 128 and output buffers 130 of the slaves and master circuit.
In FIG. 2, an example of a dedicated scan cell consists of multiplexer 1 (MX1) 202, memory 1 (M1) 204, memory 2 (M2) 206, and multiplexer 1 (MX2) 208. This scan cell is similar to scan cells described in IEEE standard 1149.1, so only a brief description will be provided. During operation in a functional mode, functional data passes from the functional data input (FDI) 212 to the functional data output (FDO) 214. In a functional mode, control inputs 210 to the scan cell can: (1) cause FDI data to be loaded into M1 via MX1 during a capture operation; (2) scan data from TDI 216 through MX1 and M1 to TDO 218 during a shift operation; and (3) cause data in M1 to be loaded into M2 during an update operation. Neither the capture, shift, nor update operation disturbs the functional data passing between FDI and FDO. Thus the scan cell of FIG. 2 can be accessed and pre-loaded with test data while the cell is in functional mode. The data scan cell (D) associated with the D31 output of slave 1 104 has connections corresponding to the FDI 212, TDI 216, FDO 214, and TDO 218 signal connections of the FIG. 2 scan cell.
During a functional mode of operation of the circuit in FIG. 1, data is transferred from one of the slaves to the master via a 32-bit data bus (D0-31), indicated by the wired bus connections 126. In a functional mode the scan cells are transparent, allowing functional control and data signals to pass freely through the cells. In this example, the master enables slave 1 to transfer data by the ENA1 control signal, which is output from the master to slave 1. Likewise the master enables slave 2 to transfer data by the ENA2 control signal, which is output from the master to slave 2. While only two slave circuits are shown, any number could be similarly connected to and operated by the master. Since all the scan cells of the scan paths 108-112 are dedicated for test, they can be scanned from TDI to TDO without disturbing the functional mode of the FIG. 1 circuit
As mentioned, being able to scan data into the scan paths during functional mode allows pre-loading an initial test pattern into the scan paths. The initial test pattern establishes both a data test pattern in the data scan cells (D) and a control test pattern in the control scan cells (C). By pre-loading an initial test pattern into the scan paths, the circuits can safely transition from a functioning mode to a test mode without concern over bus contention between the slave circuit's data busses. For example, the ENA1 122 and ENA2 124 control scan cells (C) can be pre-loaded with control data to insure that only one of the slave's D0-31 data busses is enabled to drive the wired bus connection 126. Maintaining output drive on one of the slave data busses upon entry into test mode prevents the wired data bus 126 from entering into a floating. (i.e. 3-state) condition. Preventing bus 126 from floating is desirable since a floating input to input buffers 128 of master 102 could cause a high current condition.
When test mode is entered, functional operation of the master and slave circuits stop and the scan cells in the scan paths take control of the master and slave circuit's data and control signal paths. A data scan cell (D) exists on each of the 32-bit data signal paths of each circuit 102-106, and a control scan cell (C) exists on each of the ENA1 and ENA2 control paths of each circuit 102-106. Having dedicated data and control scan cells located as shown in FIG. 1, enables safe test entry and easy interconnect testing of the wiring between the master and slave circuits when the scan paths are placed in test mode. During interconnect test mode, a capture, shift, and update control sequence, such as that defined in IEEE standard 1149.1, can be used to control the scan paths.
To prevent contention between slave 1 and slave 2 data outputs 126 during the capture, shift, and update control sequence, the 3-state control outputs 118-120 of the ENA1 and ENA2 control scan cells 122-124 do not ripple during the capture and shift part of the control input sequence. This is accomplished by having the data in M2 of FIG. 2 be output, via MX2, during the capture and shift operation. Only during the update part of the control input sequence are the outputs 118-120 of the control scan cells 122-124 allowed to change state by new data being loaded into M2. Similarly, the outputs from the data scan cells (D) do not ripple during capture and shift operations, but rather change state only during the update part of the control input sequence.
In FIG. 3, a prior art example of a shared boundary scan path exists around a master 302 and slave circuits 304-306. As in FIG. 1, the scan paths 308-312 around each circuit are connected together serially and to a test data input (TDI), which supplies test data to the scan paths, and a test data output (TDO), which retrieves data from the scan paths. The scan paths of FIG. 3 are designed using shared scan cells (C) and (D), i.e. the scan cell memory is shared for both test and functional purposes. As an aid to indicate use of shared scan cells as opposed to dedicated scan cells, the shared scan cells of FIG. 3 and subsequent figures are shown positioned outside the boundary scan paths 308-312 and in the functional circuits. The dedicated scan cells of FIG. 1 were shown positioned inside the boundary scan paths 108-112. Again, for simplification, only a portion of each circuit's boundary scan path is shown.
In FIG. 4, an example of a conventional shared scan cell consists of a multiplexer (MX) 402 and a memory (M) 404. During a functional mode of operation, control inputs 406 form a path between FDI 408 and the data input of M 404 via MX 402, to allow functional data to be clocked from FDI to FDO 410. During a test mode, the control inputs 406 cause FDI data to be clocked into M via MX during a capture operation, and cause test data to be clocked from TDI 412 to TDO 414 during a shift operation. Since M 404 is used functionally, it cannot be accessed and pre-loaded with test data as can the scan cell of FIG. 2. Thus the ability to access and pre-load test data while the master and slave circuits of FIG. 3 operate functionally is one of the key distinctions between dedicated (FIG. 2) and shared (FIG. 4) scan cells.
In FIG. 3, the data scan cell associated with the D31 output of slave 1 304 is labeled to indicate the FDI 408, TDI 412, FDO 410, and TDO 414 signal connections of the FIG. 4 scan cell.
During the functional mode of the circuit in FIG. 3, as in FIG. 1, data is transferred from one of the slaves to the master via the 32-bit data bus (D0-31) through shared connections 326. The master enables data transfer from slave 1 or slave 2 via the ENA1 and ENA2 control signals, respectively. Since the scan cells of the scan paths are shared and used functionally, they cannot be scanned from TDI to TDO without disturbing the functional mode of the circuits. Not being able to scan data into the scan paths during functional mode prevents pre-loading an initial test pattern into the scan paths.
By not being able to pre-load an initial test pattern into the scan paths, the slave circuits are put at risk of not safely transitioning into the test mode from the functional mode. This situation occurs due to the timing domains of the functional and test modes not being synchronous to one another, which results in asynchronous functional to test mode switching.
For example, if the circuits of FIG. 3 switched from the functional mode timing domain to a test mode timing domain, a possibility exists that the D0-31 output buffers of slave 1 and 2 could both be enabled as a result of an asynchronous mode switch that caused scan cell ENA1 322 and scan cell ENA2 324 to both output enable conditions on wires 318 and 320. This would force a voltage contention situation between slave 1 and 2, resulting in the output buffers being damaged or destroyed. This voltage contention situation does not occur in the boundary scan path of FIG. 1 since an initial safe test pattern is pre-loaded into the scan cells prior to the functional to test mode switching step.
Once in a test mode, the scan path of FIG. 3 can be accessed to shift in test data. During shift operations the outputs 318-320 of the control scan cells 322-324 ripple as data shifts through the cells. This output ripple from the control scan cells can cause the D0-31 output buffers of the slaves to be enabled and disabled during the shift operation. This control output ripple causes the output buffers of slaves 1 and 2 to be simultaneously enabled, again creating bus contention between the slaves. This voltage contention situation does not occur in the boundary scan oath of FIG. 1 since M 206 maintains a safe control output via MX 208, during shift operations.
In FIG. 5, one prior art technique prevents the above-mentioned two voltage contention situations. The technique is based on providing additional circuitry and control inputs to enable or disable the slave's output buffers during test mode entry and again during each test mode shift operation. A signal gating circuit 528 is inserted into signal path 518 of slave 504 and a signal gating circuit 530 is inserted into signal path 520 of slave 506. A control signal C1 532 is added as an input to circuits 528 and 530. When C1 is in a first state, the ENA1 and ENA2 outputs from scan cells 522 and 524 are allowed to pass through circuits 528 and 530 to enable or disable the output buffers of slaves 504 and 506. However, when C1 is in a second state, the outputs of circuits 528 and 530 are forced, independent of ENA1 and ENA2, to disable the output buffers of slaves 504 and 506. By controlling C1 to the second state during the transition from functional mode to test mode, the first above mentioned voltage contention situation can be avoided. By again controlling C1 to the second state during each shift operation that occurs during test mode, the second above mentioned voltage contention situation can be avoided.
While the technique described above solves the voltage contention situations, it does so by introducing a floating (i.e. 3-state) condition on data bus 526. As described above, the output buffers of slaves 504 and 506 are disabled during test mode entry and during each shift operation. With the output buffers disabled, data bus 526 is not driven and may float to a voltage level that could turn on both input transistors of the input buffers of master 502. This could result in a low impedance path between the master's supply and ground voltages, potentially damaging or destroying the input buffers of master 502.